Growth in Floating-Point applications and mainly its usage in reconfigurable hardware have made it critical to optimize floating-point units. A divider is of particular interest because the design space is large and divider usage in applications varies widely. The design presented in this paper covers a range of performance, area, and throughput constraints. Floating-point numbers can be represented by single and double precision respectively. A design for a single-precision floating-point divider was done in Verilog and was synthesized using Xilinx and Synopsys tool. The path delay, device utilization was also determined successfully.
Software Language Used: Verilog HDL
Software Tool Used: Xilinx IDE.