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Design of VGA Display System Based on CPLD and SRAM


Most of the logic analyzer uses C.P.U. to display the output on the monitor. The problem of existing logic analyzer is that it requires software in order to function properly. Furthermore, it is not portable. Hence to eliminate the use of CPU to display the data on the monitor VGA display based on the CPLD and SRAM is necessary. As a video image display interface standard, VGA interface has been widely used in the embedded system. Due to the lack of professional VGA display controller in most embedded systems, splash screen, even blank screen problems may appear while displaying the high-resolution video image. The design illustrates the implementing method of VGA display controller, which combines CPLD and SRAM. First, the design stores data that gets from the processor in the SRAM and then read them out in form of VGA display interface standard into D/A converter which will convert the data into analog signals to display. The whole operation above is controlled by CPLD. So such a design can effectively solve the problems caused by insufficient bandwidth in the displaying, what’s more, it can reduce the pressure on the CPU.

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VGA display is Video Graphics Array and it comes in an account in 1987. It displays approximately 256 simultaneous colors. Also, it has 640 X 480=307,200 pixels maximum resolution. But with this resolution graphic card able to generate only 16 colors. This design is used to eliminate the use of CPU to display the textual data. The design will be developed using the programmable logic device- based logic analyzer. And also it is used to combine a video display controller with an SRAM memory controller. And this design used to create a Video frame buffer.

The SRAM should be 256Kx16 CMOS static ram memories. And these memories are used to store images that will be displayed on the VGA screen Now data from the logic analyzer designed by others is combined with this design. The final goal is by using single-chip CPLD and SRAM based logic analyzers which display the output measurement to monitor without interfaced with CPU. CPLD includes the generation of VGA timing signal, finite state machine, and logic control.

Software Language Used: Verilog HDL

Software Tool Used: Xilinx IDE.

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