Arithmetic is the basic operation in everyday life which includes an operation such as addition, subtraction, multiplication, and division. To keep a check on the proper working on this arithmetic operation, an Arithmetic logical unit is the most important element of a system (ALU). On the basis of a number of clock cycles required in performing each arithmetic operation performance of the pipelined ALU will be checked out. Floating-point representation is based on the IEEE standard 754. A pipelined ALU is proposed in this paper simulating four arithmetic operations namely addition, subtraction, multiplication, division in the VHDL environment.
Software Language Used: Verilog HDL
Software Tool Used: Xilinx IDE.