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Verilog Implementation of the IEEE 754 Floating Point Exponential Function

3,600.00 3,000.00

The IEEE-754 floating-point standard, used in nearly alu floating-point applications, is considered one of the most important standards. Deep datapath and algorithm complexity have made the verification of such floating-point units a very hard task.

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The IEEE-754 floating-point standard, used in nearly al1 floating-point applications, is considered one of the most important standards. Deep datapath and algorithm complexity have made the verification of such floating-point units a very hard task. Most simulation and reachability analysis verification tools faü to verify a circuit with a deep datapath like most industrial floating-point units. Theorem proving, however, offers a better solution to handle such verification.

In this project, we have formalized and verified a hardware implementation of the IEEE-754 Table-Driven floating-point exponential function algorithm using the HOL theorem prover. The high ability of abstraction in the HOL verification system allows its use for the verification task over the whole design path of the circuit, starting from the gate level implementation of the circuit up to a higher level behavioral specification. To achieve this goal, we have used both hierarchical and modular approaches for modeling and verifying the floating-point exponential function in HOL.

Software Language Used: Verilog HDL

Software Tool Used: Xilinx IDE.

The verification of floating-point circuits has always been an important part of the process verification icon. The importance of arithmetic circuit verification was illustrated by the famous floa~g-point division bug in Intel’s Pentium processor. Floating-point algorithms are usually very complicated. They are composed of many modules where the smallest flaw in design or implementation can cause a very hard-to-discover bug, as occurred in Intel’s case. Traditional approaches to verifying floating-point circuits are based on simulation. However, these approaches cannot exhaustively cover the input space of the circuits.

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