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VHDL Implementation of 8 bit Vedic Multiplier

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The fast and low power multipliers are required in small size wireless sensor networks and many other DSP (Digital Signal Processing) applications. In the implementation of many algorithms such as Fast Fourier Transforms (FFT), Discrete Fourier Transform (DFT) etc, high speed and low power multipliers are of critical importance.

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The multiplier is an essential functional block of a microprocessor because multiplication is needed to be performed repeatedly in almost all scientific calculations. Therefore, the design of fast and low power binary multiplier is very important, particularly for Digital Signal Processors. This paper describes a design of fast and low power 8-bit multiplier architecture which implements Urdhva-tiryakbyham sutra of the Vedic method of multiplication. The multiplier is designed in 180nm technology using a cadence EDA tool and simulated using specter simulator and found to be working correctly and results have been compared for pre-layout and post-layout analysis. It is shown that the implementation of multiplier using the Vedic sutra leads to a very compact layout leading to a significantly smaller Silicon area and a very small contribution of interconnections to the overall propagation delay of the multiplier. The performance of the proposed multiplier has been compared with those of other multipliers reported in the literature.

The fast and low power multipliers are required in small size wireless sensor networks and many other DSP (Digital Signal Processing) applications. In the implementation of many algorithms such as Fast Fourier Transforms (FFT), Discrete Fourier Transform (DFT), etc, high speed and low power multipliers are of critical importance. Two basic multiplication methods namely the Booth multiplication algorithm and the Array multiplication algorithm have been used for the design of multipliers. It has been reported that the Booth multiplication algorithm provides for faster multiplication only if operand sizes are small. For fast multiplication, array multipliers are used. This method provides for faster multiplication because all the partial products are obtained simultaneously using AND gates. In an array or parallel multipliers, the speed of multiplication (as well as power dissipation) is dominantly controlled by the propagation delay of the full/half adders used for the addition of partial products. The schemes for efficient addition of partial products such as Wallace tree; Dadda tree and use of compressors have been reported in the literature. Wallace tree multiplier gives the best performance but suffers from the disadvantage of highly irregular structure which means that it requires a larger area and involves a complex interconnection which is more difficult to implement.

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